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stm32/rcc: fix pll enum naming on f4, f7.

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This commit is contained in:
Dario Nieuwenhuis 2023-11-13 01:53:27 +01:00
parent f00e97a5f1
commit 2376b3bdfa
10 changed files with 21 additions and 21 deletions
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10
embassy-stm32/src/rcc/f4f7.rs
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@ -1,7 +1,7 @@
use crate::pac::pwr::vals::Vos; use crate::pac::pwr::vals::Vos;
pub use crate::pac::rcc::vals::{ pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp, Pllq, Pllr, Pllsrc as PllSource, Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
Ppre as APBPrescaler, Sw as Sysclk, Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
}; };
use crate::pac::{FLASH, PWR, RCC}; use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks}; use crate::rcc::{set_freqs, Clocks};
@ -49,11 +49,11 @@ pub struct Pll {
pub mul: PllMul, pub mul: PllMul,
/// PLL P division factor. If None, PLL P output is disabled. /// PLL P division factor. If None, PLL P output is disabled.
pub divp: Option<Pllp>, pub divp: Option<PllPDiv>,
/// PLL Q division factor. If None, PLL Q output is disabled. /// PLL Q division factor. If None, PLL Q output is disabled.
pub divq: Option<Pllq>, pub divq: Option<PllQDiv>,
/// PLL R division factor. If None, PLL R output is disabled. /// PLL R division factor. If None, PLL R output is disabled.
pub divr: Option<Pllr>, pub divr: Option<PllRDiv>,
} }
/// Configuration of the core clocks /// Configuration of the core clocks

2
examples/stm32f4/src/bin/eth.rs
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@ -42,7 +42,7 @@ async fn main(spawner: Spawner) -> ! {
config.rcc.pll = Some(Pll { config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4, prediv: PllPreDiv::DIV4,
mul: PllMul::MUL180, mul: PllMul::MUL180,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz. divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
divq: None, divq: None,
divr: None, divr: None,
}); });

4
examples/stm32f4/src/bin/sdmmc.rs
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@ -30,8 +30,8 @@ async fn main(_spawner: Spawner) {
config.rcc.pll = Some(Pll { config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4, prediv: PllPreDiv::DIV4,
mul: PllMul::MUL168, mul: PllMul::MUL168,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
divr: None, divr: None,
}); });
config.rcc.ahb_pre = AHBPrescaler::DIV1; config.rcc.ahb_pre = AHBPrescaler::DIV1;

4
examples/stm32f4/src/bin/usb_ethernet.rs
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@ -56,8 +56,8 @@ async fn main(spawner: Spawner) {
config.rcc.pll = Some(Pll { config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4, prediv: PllPreDiv::DIV4,
mul: PllMul::MUL168, mul: PllMul::MUL168,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
divr: None, divr: None,
}); });
config.rcc.ahb_pre = AHBPrescaler::DIV1; config.rcc.ahb_pre = AHBPrescaler::DIV1;

4
examples/stm32f4/src/bin/usb_raw.rs
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@ -85,8 +85,8 @@ async fn main(_spawner: Spawner) {
config.rcc.pll = Some(Pll { config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4, prediv: PllPreDiv::DIV4,
mul: PllMul::MUL168, mul: PllMul::MUL168,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
divr: None, divr: None,
}); });
config.rcc.ahb_pre = AHBPrescaler::DIV1; config.rcc.ahb_pre = AHBPrescaler::DIV1;

4
examples/stm32f4/src/bin/usb_serial.rs
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@ -32,8 +32,8 @@ async fn main(_spawner: Spawner) {
config.rcc.pll = Some(Pll { config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4, prediv: PllPreDiv::DIV4,
mul: PllMul::MUL168, mul: PllMul::MUL168,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
divr: None, divr: None,
}); });
config.rcc.ahb_pre = AHBPrescaler::DIV1; config.rcc.ahb_pre = AHBPrescaler::DIV1;

2
examples/stm32f7/src/bin/eth.rs
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@ -43,7 +43,7 @@ async fn main(spawner: Spawner) -> ! {
config.rcc.pll = Some(Pll { config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4, prediv: PllPreDiv::DIV4,
mul: PllMul::MUL216, mul: PllMul::MUL216,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
divq: None, divq: None,
divr: None, divr: None,
}); });

4
examples/stm32f7/src/bin/sdmmc.rs
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@ -26,8 +26,8 @@ async fn main(_spawner: Spawner) {
config.rcc.pll = Some(Pll { config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4, prediv: PllPreDiv::DIV4,
mul: PllMul::MUL216, mul: PllMul::MUL216,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz divq: Some(PllQDiv::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
divr: None, divr: None,
}); });
config.rcc.ahb_pre = AHBPrescaler::DIV1; config.rcc.ahb_pre = AHBPrescaler::DIV1;

4
examples/stm32f7/src/bin/usb_serial.rs
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@ -32,8 +32,8 @@ async fn main(_spawner: Spawner) {
config.rcc.pll = Some(Pll { config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4, prediv: PllPreDiv::DIV4,
mul: PllMul::MUL216, mul: PllMul::MUL216,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz divq: Some(PllQDiv::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
divr: None, divr: None,
}); });
config.rcc.ahb_pre = AHBPrescaler::DIV1; config.rcc.ahb_pre = AHBPrescaler::DIV1;

4
tests/stm32/src/common.rs
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@ -271,7 +271,7 @@ pub fn config() -> Config {
config.rcc.pll = Some(Pll { config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4, prediv: PllPreDiv::DIV4,
mul: PllMul::MUL180, mul: PllMul::MUL180,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz. divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
divq: None, divq: None,
divr: None, divr: None,
}); });
@ -292,7 +292,7 @@ pub fn config() -> Config {
config.rcc.pll = Some(Pll { config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4, prediv: PllPreDiv::DIV4,
mul: PllMul::MUL216, mul: PllMul::MUL216,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz. divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz.
divq: None, divq: None,
divr: None, divr: None,
}); });