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nrf/qspi: add nrf53 support.
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9eb65b11cb
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@ -250,6 +250,9 @@ embassy_hal_common::peripherals! {
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TIMER1,
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TIMER2,
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// QSPI
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QSPI,
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// GPIOTE
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GPIOTE_CH0,
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GPIOTE_CH1,
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@ -393,6 +396,8 @@ impl_timer!(TIMER0, TIMER0, TIMER0);
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impl_timer!(TIMER1, TIMER1, TIMER1);
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impl_timer!(TIMER2, TIMER2, TIMER2);
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impl_qspi!(QSPI, QSPI, QSPI);
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impl_pin!(P0_00, 0, 0);
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impl_pin!(P0_01, 0, 1);
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#[cfg(feature = "nfc-pins-as-gpio")]
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@ -58,7 +58,7 @@ pub mod ppi;
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pub mod pwm;
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#[cfg(not(any(feature = "nrf51", feature = "_nrf9160", feature = "_nrf5340")))]
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pub mod qdec;
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#[cfg(feature = "nrf52840")]
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#[cfg(any(feature = "nrf52840", feature = "_nrf5340-app"))]
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pub mod qspi;
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#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
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pub mod rng;
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@ -133,25 +133,26 @@ impl<'d, T: Instance, const FLASH_SIZE: usize> Qspi<'d, T, FLASH_SIZE> {
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let r = T::regs();
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sck.set_high();
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csn.set_high();
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io0.set_high();
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io1.set_high();
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io2.set_high();
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io3.set_high();
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sck.conf().write(|w| w.dir().output().drive().h0h1());
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csn.conf().write(|w| w.dir().output().drive().h0h1());
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io0.conf().write(|w| w.dir().output().drive().h0h1());
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io1.conf().write(|w| w.dir().output().drive().h0h1());
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io2.conf().write(|w| w.dir().output().drive().h0h1());
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io3.conf().write(|w| w.dir().output().drive().h0h1());
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macro_rules! config_pin {
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($pin:ident) => {
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$pin.set_high();
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$pin.conf().write(|w| {
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w.dir().output();
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w.drive().h0h1();
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#[cfg(feature = "_nrf5340-s")]
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w.mcusel().peripheral();
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w
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});
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r.psel.$pin.write(|w| unsafe { w.bits($pin.psel_bits()) });
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};
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}
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r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
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r.psel.csn.write(|w| unsafe { w.bits(csn.psel_bits()) });
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r.psel.io0.write(|w| unsafe { w.bits(io0.psel_bits()) });
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r.psel.io1.write(|w| unsafe { w.bits(io1.psel_bits()) });
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r.psel.io2.write(|w| unsafe { w.bits(io2.psel_bits()) });
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r.psel.io3.write(|w| unsafe { w.bits(io3.psel_bits()) });
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config_pin!(sck);
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config_pin!(csn);
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config_pin!(io0);
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config_pin!(io1);
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config_pin!(io2);
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config_pin!(io3);
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r.ifconfig0.write(|w| {
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w.addrmode().variant(config.address_mode);
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