mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-22 06:42:32 +00:00
Support for multibuffer, but without overflow check
This commit is contained in:
Dirk Fuhrmann
parent
242347b0a9
commit
16ec38c38a
@ -3,7 +3,7 @@
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use core::future::Future;
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use core::pin::Pin;
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use core::ptr;
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use core::sync::atomic::{fence, Ordering};
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use core::sync::atomic::{fence, AtomicBool, AtomicU8, Ordering};
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use core::task::{Context, Poll};
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use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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@ -33,7 +33,7 @@ impl Default for TransferOptions {
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}
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}
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impl From<WordSize> for vals::Dw {
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impl From<WordSize> for vals::ChTr1Dw {
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fn from(raw: WordSize) -> Self {
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match raw {
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WordSize::OneByte => Self::BYTE,
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@ -45,11 +45,19 @@ impl From<WordSize> for vals::Dw {
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pub(crate) struct ChannelState {
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waker: AtomicWaker,
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is_lli_mode: AtomicBool,
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transfer_in: AtomicU8,
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transfer_out: AtomicU8,
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transfer_size: AtomicU8,
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}
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impl ChannelState {
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pub(crate) const NEW: Self = Self {
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waker: AtomicWaker::new(),
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is_lli_mode: AtomicBool::new(false),
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transfer_in: AtomicU8::new(0),
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transfer_out: AtomicU8::new(0),
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transfer_size: AtomicU8::new(0),
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};
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}
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@ -64,6 +72,119 @@ pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: P
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crate::_generated::init_gpdma();
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}
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/// Linked List Table
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#[derive(Debug)]
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pub struct LliTable<W: Word, const MEMS: usize, const BUFLEN: usize> {
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addrs: [&'static [W; BUFLEN]; MEMS],
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items: &'static mut [LliItem; MEMS],
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option: LliOption,
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}
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impl<W: Word, const MEMS: usize, const BUFLEN: usize> LliTable<W, MEMS, BUFLEN> {
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/// sets the buffer addresses
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///
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/// const ADC_BUFFERS: usize = 2;
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/// const ADC1_CHANNELS: usize = 8;
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/// static mut ADC1_BUF: [[u16;8];ADC_BUFFERS] = [[0u16;ADC1_CHANNELS];ADC_BUFFERS];
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/// static mut ADC1_LLIITEMS: [LliItem;ADC_BUFFERS] = [LliItem { dar: 0, llr: 0 }; ADC_BUFFERS];
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/// static ADC1_LLITABLE: StaticCell<LliTable<u16, ADC_BUFFERS, ADC1_CHANNELS>> = StaticCell::new();
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/// // creates an array of buffer addresses
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/// let adc1_lli = unsafe { ADC1_BUF.iter().map(|w| *addr_of!(w)).collect::<Vec<&[u16;ADC1_CHANNELS]>>().as_slice().try_into().unwrap() };
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///
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/// let lli_table = unsafe { ADC1_LLITABLE.init(LliTable::new(adc1_lli, &mut *addr_of_mut!(ADC1_LLIITEMS), LliOption::Repeated)) };
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///
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/// // start the dma with
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/// let dma = Transfer::new_read_with_lli(...)
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///
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/// // the data can read with get_next_buffer(..)
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///
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pub fn new(
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addrs: [&'static [W; BUFLEN]; MEMS],
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lli_items: &'static mut [LliItem; MEMS],
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option: LliOption,
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) -> Self {
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assert!(MEMS > 1);
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assert!(BUFLEN > 0);
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//map the buffer startaddr to lli
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for (index, buf) in addrs.iter().enumerate() {
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let (ptr, mut len) = super::slice_ptr_parts(*buf);
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len *= W::size().bytes();
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assert!(len > 0 && len <= 0xFFFF);
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lli_items[index].dar = ptr as u32;
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}
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let mut this = Self {
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items: lli_items,
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addrs,
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option,
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};
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this.fixing_memory();
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this
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}
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/// Create the Linked List
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fn fixing_memory(&mut self) {
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// create linked list
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for i in 0..MEMS - 1 {
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let lli_plus_one = ptr::addr_of!(self.items[i + 1]) as u16;
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self.items[i].set_llr(lli_plus_one as u16);
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}
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match self.option {
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LliOption::Repeated => self.items[MEMS - 1].set_llr(ptr::addr_of!(self.items[0]) as u16), // Connect the end and the beginning
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LliOption::Single => self.items[MEMS - 1].llr = 0,
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}
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}
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/// get the next Buffer
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pub fn get_next_buffer(&self, dma: &Transfer) -> Option<&&[W; BUFLEN]> {
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let state = dma.get_lli_state();
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let i = state.transfer_in.load(Ordering::Relaxed);
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let o = state.transfer_out.load(Ordering::Relaxed);
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match i == o {
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true => None,
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false => {
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//defmt::info!("DMA GET BUF {}", o);
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let result = self.addrs.get((o as usize) % MEMS);
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let _ = state
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.transfer_out
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.fetch_update(Ordering::Relaxed, Ordering::Relaxed, |v| {
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if v >= state.transfer_size.load(Ordering::Relaxed) {
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Some(0)
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} else {
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Some(v + 1)
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}
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});
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result
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}
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}
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}
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}
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#[derive(Debug, Copy, Clone, Default)]
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#[repr(C)]
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/// Linked List Item
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pub struct LliItem {
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/// Data Start Address
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pub dar: u32,
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/// Linked List
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pub llr: u32,
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}
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#[allow(unused)]
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impl LliItem {
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fn set_llr(&mut self, la: u16) {
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// set la, uda and ull
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self.llr = (la as u32) | 1u32 << 27 | 1u32 << 16;
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}
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}
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#[derive(Debug)]
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/// Definition for the end of the linked list
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pub enum LliOption {
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/// The end of the list is linked to the beginning
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Repeated,
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/// the list is only processed once
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Single,
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}
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impl AnyChannel {
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/// Safety: Must be called with a matching set of parameters for a valid dma channel
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pub(crate) unsafe fn on_irq(&self) {
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@ -89,106 +210,29 @@ impl AnyChannel {
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}
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if sr.suspf() || sr.tcf() {
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// disable all xxIEs to prevent the irq from firing again.
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ch.cr().write(|_| {});
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if state.is_lli_mode.load(Ordering::Relaxed) {
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let _ = state
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.transfer_in
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.fetch_update(Ordering::Relaxed, Ordering::Relaxed, |v| {
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if v >= state.transfer_size.load(Ordering::Relaxed) {
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Some(0)
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} else {
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Some(v + 1)
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}
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});
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ch.fcr().modify(|reg| reg.set_tcf(true));
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//defmt::info!("DMA SET BUF {}", state.transfer_in.load(Ordering::Relaxed));
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} else {
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// disable all xxIEs to prevent the irq from firing again.
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ch.cr().write(|_| {});
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// Wake the future. It'll look at tcf and see it's set.
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state.waker.wake();
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// Wake the future. It'll look at tcf and see it's set.
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state.waker.wake();
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}
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}
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}
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}
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/// Linked List Table
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#[derive(Debug)]
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pub struct LliTable<'a, W: Word, const MEMS: usize, const BUFLEN: usize> {
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addrs: &'a [&'a [W; BUFLEN]; MEMS],
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items: [LliItem; MEMS],
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size: WordSize,
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}
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impl<'a, W: Word, const MEMS: usize, const BUFLEN: usize> LliTable<'a, W, MEMS, BUFLEN> {
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/// sets the buffer addresses
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///
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/// let buf0 = [0u16; 6];
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/// let buf1 = [0u16; 6];
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/// let bufs = [&buf0,&buf1];
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/// let lli_table = LliTable::new(&bufs);
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///
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/// // after move or copy use fixing_in_mem(LliOption)
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///
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pub fn new(addrs: &'a [&'a [W; BUFLEN]; MEMS]) -> Self {
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assert!(MEMS > 1);
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assert!(BUFLEN > 0);
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let mut items = [LliItem::default(); MEMS];
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//map the buffer startaddr to lli
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for (index, buf) in addrs.into_iter().enumerate() {
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let (ptr, mut len) = super::slice_ptr_parts(*buf);
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len *= W::size().bytes();
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assert!(len > 0 && len <= 0xFFFF);
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items[index].dar = ptr as u32;
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}
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Self {
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items,
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size: W::size(),
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addrs,
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}
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}
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/// Create the Linked List
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/// use it after a copy or move
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pub fn fixing_in_mem(&mut self, option: LliOption) {
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// create linked list
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for i in 0..MEMS - 1 {
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let lli_plus_one = ptr::addr_of!(self.items[i + 1]) as u16;
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let lli = &mut self.items[i];
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lli.set_llr(lli_plus_one);
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}
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match option {
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LliOption::Repeated => self.items[MEMS - 1].set_llr(ptr::addr_of!(self.items[0]) as u16), // Connect the end and the beginning
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LliOption::Single => self.items[MEMS - 1].llr = 0,
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}
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}
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/// the memory width
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pub fn get_size(&self) -> WordSize {
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self.size
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}
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/// get the last address from the buffer for double Buffer mode
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/// Buffer 0 and 1 must not be the same
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pub fn find_last_buffer_in_double_buffer_mode(&self, dar: u32) -> &[W; BUFLEN] {
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assert!(MEMS == 2);
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match self.items[0].dar == dar {
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true => self.addrs[1],
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_ => self.addrs[0],
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}
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}
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}
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#[derive(Debug, Copy, Clone, Default)]
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/// Linked List Item
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pub struct LliItem {
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/// Data Start Address
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pub dar: u32,
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/// Linked List
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pub llr: u32,
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}
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#[allow(unused)]
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impl LliItem {
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fn set_llr(&mut self, la: u16) {
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// set la, uda and ull
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self.llr = (la as u32) | 1u32 << 27 | 1u32 << 16;
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}
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}
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/// Definition for the end of the linked list
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pub enum LliOption {
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/// The end of the list is linked to the beginning
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Repeated,
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/// the list is only processed once
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Single,
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}
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/// DMA transfer.
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#[must_use = "futures do nothing unless you `.await` or poll them"]
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pub struct Transfer<'a> {
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@ -196,6 +240,76 @@ pub struct Transfer<'a> {
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}
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impl<'a> Transfer<'a> {
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/// Create a new read DMA transfer (peripheral to memory). with linked list
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/// The transfer starts at buf0 and moves to the next buffer after a transfer, etc
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/// The LLI Table can be configured as a single or repeated transfer
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/// the buffer switching is done in Hardware
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pub unsafe fn new_read_with_lli<W: Word, const M: usize, const N: usize>(
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channel: impl Peripheral<P = impl Channel> + 'a,
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request: Request,
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peri_addr: *mut W,
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llit: &LliTable<W, M, N>,
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_options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
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let data_size = W::size();
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let info = channel.info();
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let ch = info.dma.ch(info.num);
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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let this = Self { channel };
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(&*this.channel, request);
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ch.cr().write(|w| w.set_reset(true));
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ch.fcr().write(|w| w.0 = 0xFFFF_FFFF); // clear all irqs
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ch.tr1().write(|w| {
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w.set_sdw(data_size.into());
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w.set_ddw(data_size.into());
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w.set_sinc(false);
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w.set_dinc(true);
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});
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ch.tr2().write(|w| {
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w.set_dreq(vals::ChTr2Dreq::SOURCEPERIPHERAL);
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w.set_reqsel(request);
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});
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ch.sar().write_value(peri_addr as _); // Peripheral Addr
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let llis_base_addr = ptr::addr_of!(llit.items) as u32;
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ch.lbar().write(|reg| reg.set_lba((llis_base_addr >> 16) as u16)); // linked high addr
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ch.br1().write(|reg| reg.set_bndt((N * W::size().bytes()) as u16));
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ch.dar().write(|reg| *reg = llit.items[0].dar);
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ch.llr().write(|reg| reg.0 = llit.items[0].llr); // Set Start llr
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let state = &STATE[this.channel.id as usize];
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state.is_lli_mode.store(true, Ordering::Relaxed);
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state.transfer_in.store(0, Ordering::Relaxed);
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state.transfer_out.store(0, Ordering::Relaxed);
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state.transfer_size.store(M as _, Ordering::Relaxed);
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ch.cr().write(|w| {
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// Enable interrupts
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w.set_tcie(true);
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w.set_useie(true);
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w.set_dteie(true);
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w.set_suspie(true);
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// Start it
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w.set_en(true);
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});
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this
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}
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/// get the channel state
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fn get_lli_state(&self) -> &ChannelState {
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&STATE[self.channel.id as usize]
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}
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/// Create a new read DMA transfer (peripheral to memory).
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pub unsafe fn new_read<W: Word>(
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channel: impl Peripheral<P = impl Channel> + 'a,
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@ -327,8 +441,8 @@ impl<'a> Transfer<'a> {
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});
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ch.tr2().write(|w| {
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w.set_dreq(match dir {
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Dir::MemoryToPeripheral => vals::Dreq::DESTINATIONPERIPHERAL,
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Dir::PeripheralToMemory => vals::Dreq::SOURCEPERIPHERAL,
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Dir::MemoryToPeripheral => vals::ChTr2Dreq::DESTINATIONPERIPHERAL,
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Dir::PeripheralToMemory => vals::ChTr2Dreq::SOURCEPERIPHERAL,
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});
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w.set_reqsel(request);
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});
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@ -362,74 +476,6 @@ impl<'a> Transfer<'a> {
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this
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}
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/// Create a new read DMA transfer (peripheral to memory). with linked list
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/// The transfer starts at buf0 and moves to the next buffer after a transfer, etc
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/// The last LLI entry has a link to the first buffer
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/// the buffer switching is in Hardware
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pub unsafe fn new_read_with_lli<W: Word, const M: usize, const N: usize>(
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channel: impl Peripheral<P = impl Channel> + 'a,
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request: Request,
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peri_addr: *mut W,
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llit: &mut LliTable<'a, W, M, N>,
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lli_option: LliOption,
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_options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
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let data_size = W::size();
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let info = channel.info();
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let ch = info.dma.ch(info.num);
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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let this = Self { channel };
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(&*this.channel, request);
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ch.cr().write(|w| w.set_reset(true));
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ch.fcr().write(|w| w.0 = 0xFFFF_FFFF); // clear all irqs
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ch.tr1().write(|w| {
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w.set_sdw(data_size.into());
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w.set_ddw(data_size.into());
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w.set_sinc(false);
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w.set_dinc(true);
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});
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ch.tr2().write(|w| {
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w.set_dreq(vals::ChTr2Dreq::SOURCEPERIPHERAL);
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w.set_reqsel(request);
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});
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ch.sar().write_value(peri_addr as _); // Peripheral Addr
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llit.fixing_in_mem(lli_option);
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let llis_base_addr = ptr::addr_of!(llit.items[0]) as u32;
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ch.lbar().write(|reg| reg.set_lba((llis_base_addr >> 16) as u16)); // linked high addr
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ch.br1().write(|reg| reg.set_bndt((N * W::size().bytes()) as u16));
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ch.dar().write(|reg| *reg = llit.items[0].dar);
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ch.llr().write(|reg| reg.0 = llit.items[0].llr); // Set Start llr
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ch.cr().write(|w| {
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// Enable interrupts
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w.set_tcie(true);
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w.set_useie(true);
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w.set_dteie(true);
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w.set_suspie(true);
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// Start it
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w.set_en(true);
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});
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this
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}
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/// get the address value from the linked address register
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pub fn get_dar_reg(&self) -> u32 {
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let info = self.channel.info();
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let ch = info.dma.ch(info.num);
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ch.dar().read()
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}
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||||
/// Request the transfer to stop.
|
||||
///
|
||||
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user