mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-21 22:32:29 +00:00
Remove support for consecutive Read operations
Due to Twim hardware limitations
This commit is contained in:
Alex Moon
parent
528a3e4355
commit
110d87bbd2
@ -105,14 +105,6 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
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let r = T::regs();
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let s = T::state();
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// Workaround for lack of LASTRX_SUSPEND short in some nRF chips
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// Do this first to minimize latency
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#[cfg(any(feature = "nrf52832", feature = "_nrf5340", feature = "_nrf9120"))]
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if r.events_lastrx.read().bits() != 0 {
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r.tasks_suspend.write(|w| unsafe { w.bits(1) });
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r.events_lastrx.reset();
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}
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if r.events_suspended.read().bits() != 0 {
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s.end_waker.wake();
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r.intenclr.write(|w| w.suspended().clear());
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@ -381,7 +373,6 @@ impl<'d, T: Instance> Twim<'d, T> {
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operations: &mut [Operation<'_>],
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tx_ram_buffer: Option<&mut [MaybeUninit<u8>; FORCE_COPY_BUFFER_SIZE]>,
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inten: bool,
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stop: bool,
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) -> Result<(), Error> {
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let r = T::regs();
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@ -401,14 +392,12 @@ impl<'d, T: Instance> Twim<'d, T> {
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r.intenclr
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.write(|w| w.suspended().clear().stopped().clear().error().clear());
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}
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#[cfg(any(feature = "nrf52832", feature = "_nrf5340", feature = "_nrf9120"))]
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r.intenclr.write(|w| w.lastrx().clear());
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match operations {
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[Operation::Read(rd_buffer), Operation::Write(wr_buffer), rest @ ..]
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if !rd_buffer.is_empty() && !wr_buffer.is_empty() =>
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{
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let stop = stop && rest.is_empty();
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let stop = rest.is_empty();
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// Set up DMA buffers.
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unsafe {
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@ -433,11 +422,9 @@ impl<'d, T: Instance> Twim<'d, T> {
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r.tasks_resume.write(|w| unsafe { w.bits(1) });
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}
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}
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[Operation::Write(wr_buffer), Operation::Read(rd_buffer), rest @ ..]
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[Operation::Write(wr_buffer), Operation::Read(rd_buffer)]
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if !wr_buffer.is_empty() && !rd_buffer.is_empty() =>
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{
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let stop = stop && rest.is_empty();
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// Set up DMA buffers.
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unsafe {
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self.set_tx_buffer(wr_buffer, tx_ram_buffer)?;
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@ -447,18 +434,9 @@ impl<'d, T: Instance> Twim<'d, T> {
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// Start write+read operation.
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r.shorts.write(|w| {
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w.lasttx_startrx().enabled();
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if stop {
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w.lastrx_stop().enabled();
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} else {
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#[cfg(not(any(feature = "nrf52832", feature = "_nrf5340", feature = "_nrf9120")))]
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w.lastrx_suspend().enabled();
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}
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w
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});
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#[cfg(any(feature = "nrf52832", feature = "_nrf5340", feature = "_nrf9120"))]
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if !stop {
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r.intenset.write(|w| w.lastrx().set());
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}
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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@ -466,9 +444,7 @@ impl<'d, T: Instance> Twim<'d, T> {
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r.tasks_resume.write(|w| unsafe { w.bits(1) });
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}
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}
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[Operation::Read(buffer), rest @ ..] => {
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let stop = stop && rest.is_empty();
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[Operation::Read(buffer)] => {
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// Set up DMA buffers.
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unsafe {
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self.set_rx_buffer(buffer)?;
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@ -476,18 +452,9 @@ impl<'d, T: Instance> Twim<'d, T> {
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// Start read operation.
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r.shorts.write(|w| {
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if stop {
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w.lastrx_stop().enabled();
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} else {
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#[cfg(not(any(feature = "nrf52832", feature = "_nrf5340", feature = "_nrf9120")))]
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w.lastrx_suspend().enabled();
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}
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w
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});
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#[cfg(any(feature = "nrf52832", feature = "_nrf5340", feature = "_nrf9120"))]
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if !stop {
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r.intenset.write(|w| w.lastrx().set());
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}
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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@ -496,16 +463,15 @@ impl<'d, T: Instance> Twim<'d, T> {
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}
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if buffer.is_empty() {
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// With a zero-length buffer, LASTRX doesn't fire (because there's no last byte!), so do the STOP/SUSPEND ourselves.
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if stop {
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// With a zero-length buffer, LASTRX doesn't fire (because there's no last byte!), so do the STOP ourselves.
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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} else {
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r.tasks_suspend.write(|w| unsafe { w.bits(1) });
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}
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}
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[Operation::Read(_), ..] => {
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panic!("Suspending after a read is not supported!");
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}
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[Operation::Write(buffer), rest @ ..] => {
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let stop = stop && rest.is_empty();
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let stop = rest.is_empty();
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// Set up DMA buffers.
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unsafe {
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@ -538,7 +504,6 @@ impl<'d, T: Instance> Twim<'d, T> {
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}
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}
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[] => {
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if stop {
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if was_suspended {
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r.tasks_resume.write(|w| unsafe { w.bits(1) });
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}
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@ -546,7 +511,6 @@ impl<'d, T: Instance> Twim<'d, T> {
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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}
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}
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}
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Ok(())
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}
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@ -557,17 +521,18 @@ impl<'d, T: Instance> Twim<'d, T> {
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match operations {
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[Operation::Read(rd_buffer), Operation::Write(wr_buffer), ..]
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| [Operation::Write(wr_buffer), Operation::Read(rd_buffer), ..]
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| [Operation::Write(wr_buffer), Operation::Read(rd_buffer)]
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if !rd_buffer.is_empty() && !wr_buffer.is_empty() =>
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{
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self.check_tx(wr_buffer.len())?;
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self.check_rx(rd_buffer.len())?;
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Ok(2)
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}
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[Operation::Read(buffer), ..] => {
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[Operation::Read(buffer)] => {
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self.check_rx(buffer.len())?;
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Ok(1)
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}
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[Operation::Read(_), ..] => unreachable!(),
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[Operation::Write(buffer), ..] => {
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self.check_tx(buffer.len())?;
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Ok(1)
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@ -583,26 +548,17 @@ impl<'d, T: Instance> Twim<'d, T> {
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/// Each buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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///
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/// If `stop` is set, the transaction will be terminated with a STOP
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/// condition and the Twim will be stopped. Otherwise, the bus will be
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/// left busy via clock stretching and Twim will be suspended.
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///
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/// The nrf52832, nrf5340, and nrf9120 do not have hardware support for
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/// suspending following a read operation therefore it is emulated by the
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/// interrupt handler. If the latency of servicing that interrupt is
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/// longer than a byte worth of clocks on the bus, the SCL clock will
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/// continue to run for one or more additional bytes. This applies to
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/// consecutive read operations, certain write-read-write sequences, or
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/// any sequence of operations ending in a read when `stop == false`.
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pub fn blocking_transaction(
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&mut self,
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address: u8,
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mut operations: &mut [Operation<'_>],
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stop: bool,
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) -> Result<(), Error> {
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/// Consecutive `Read` operations are not supported because the Twim
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/// hardware does not support suspending after a read operation. (Setting
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/// the SUSPEND task in response to a LASTRX event causes the final byte of
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/// the operation to be ACKed instead of NAKed. When the TWIM is resumed,
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/// one more byte will be read before the new operation is started, leading
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/// to an Overrun error if the RXD has not been updated, or an extraneous
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/// byte read into the new buffer if the RXD has been updated.)
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pub fn blocking_transaction(&mut self, address: u8, mut operations: &mut [Operation<'_>]) -> Result<(), Error> {
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let mut tx_ram_buffer = [MaybeUninit::uninit(); FORCE_COPY_BUFFER_SIZE];
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while !operations.is_empty() {
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self.setup_operations(address, operations, Some(&mut tx_ram_buffer), false, stop)?;
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self.setup_operations(address, operations, Some(&mut tx_ram_buffer), false)?;
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self.blocking_wait();
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let consumed = self.check_operations(operations)?;
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operations = &mut operations[consumed..];
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@ -615,10 +571,9 @@ impl<'d, T: Instance> Twim<'d, T> {
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&mut self,
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address: u8,
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mut operations: &mut [Operation<'_>],
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stop: bool,
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) -> Result<(), Error> {
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while !operations.is_empty() {
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self.setup_operations(address, operations, None, false, stop)?;
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self.setup_operations(address, operations, None, false)?;
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self.blocking_wait();
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let consumed = self.check_operations(operations)?;
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operations = &mut operations[consumed..];
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@ -634,12 +589,11 @@ impl<'d, T: Instance> Twim<'d, T> {
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&mut self,
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address: u8,
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mut operations: &mut [Operation<'_>],
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stop: bool,
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timeout: Duration,
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) -> Result<(), Error> {
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let mut tx_ram_buffer = [MaybeUninit::uninit(); FORCE_COPY_BUFFER_SIZE];
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while !operations.is_empty() {
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self.setup_operations(address, operations, Some(&mut tx_ram_buffer), false, stop)?;
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self.setup_operations(address, operations, Some(&mut tx_ram_buffer), false)?;
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self.blocking_wait_timeout(timeout)?;
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let consumed = self.check_operations(operations)?;
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operations = &mut operations[consumed..];
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@ -653,11 +607,10 @@ impl<'d, T: Instance> Twim<'d, T> {
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&mut self,
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address: u8,
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mut operations: &mut [Operation<'_>],
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stop: bool,
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timeout: Duration,
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) -> Result<(), Error> {
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while !operations.is_empty() {
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self.setup_operations(address, operations, None, false, stop)?;
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self.setup_operations(address, operations, None, false)?;
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self.blocking_wait_timeout(timeout)?;
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let consumed = self.check_operations(operations)?;
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operations = &mut operations[consumed..];
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@ -670,26 +623,17 @@ impl<'d, T: Instance> Twim<'d, T> {
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/// Each buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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///
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/// If `stop` is set, the transaction will be terminated with a STOP
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/// condition and the Twim will be stopped. Otherwise, the bus will be
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/// left busy via clock stretching and Twim will be suspended.
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///
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/// The nrf52832, nrf5340, and nrf9120 do not have hardware support for
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/// suspending following a read operation therefore it is emulated by the
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/// interrupt handler. If the latency of servicing that interrupt is
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/// longer than a byte worth of clocks on the bus, the SCL clock will
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/// continue to run for one or more additional bytes. This applies to
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/// consecutive read operations, certain write-read-write sequences, or
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/// any sequence of operations ending in a read when `stop == false`.
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pub async fn transaction(
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&mut self,
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address: u8,
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mut operations: &mut [Operation<'_>],
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stop: bool,
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) -> Result<(), Error> {
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/// Consecutive `Read` operations are not supported because the Twim
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/// hardware does not support suspending after a read operation. (Setting
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/// the SUSPEND task in response to a LASTRX event causes the final byte of
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/// the operation to be ACKed instead of NAKed. When the TWIM is resumed,
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/// one more byte will be read before the new operation is started, leading
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/// to an Overrun error if the RXD has not been updated, or an extraneous
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/// byte read into the new buffer if the RXD has been updated.)
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pub async fn transaction(&mut self, address: u8, mut operations: &mut [Operation<'_>]) -> Result<(), Error> {
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let mut tx_ram_buffer = [MaybeUninit::uninit(); FORCE_COPY_BUFFER_SIZE];
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while !operations.is_empty() {
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self.setup_operations(address, operations, Some(&mut tx_ram_buffer), true, stop)?;
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self.setup_operations(address, operations, Some(&mut tx_ram_buffer), true)?;
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self.async_wait().await;
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let consumed = self.check_operations(operations)?;
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operations = &mut operations[consumed..];
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@ -702,10 +646,9 @@ impl<'d, T: Instance> Twim<'d, T> {
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&mut self,
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address: u8,
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mut operations: &mut [Operation<'_>],
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stop: bool,
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) -> Result<(), Error> {
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while !operations.is_empty() {
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self.setup_operations(address, operations, None, true, stop)?;
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self.setup_operations(address, operations, None, true)?;
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self.async_wait().await;
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let consumed = self.check_operations(operations)?;
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operations = &mut operations[consumed..];
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@ -720,12 +663,12 @@ impl<'d, T: Instance> Twim<'d, T> {
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/// The buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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pub fn blocking_write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Error> {
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self.blocking_transaction(address, &mut [Operation::Write(buffer)], true)
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self.blocking_transaction(address, &mut [Operation::Write(buffer)])
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}
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/// Same as [`blocking_write`](Twim::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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pub fn blocking_write_from_ram(&mut self, address: u8, buffer: &[u8]) -> Result<(), Error> {
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self.blocking_transaction_from_ram(address, &mut [Operation::Write(buffer)], true)
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self.blocking_transaction_from_ram(address, &mut [Operation::Write(buffer)])
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}
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/// Read from an I2C slave.
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@ -733,7 +676,7 @@ impl<'d, T: Instance> Twim<'d, T> {
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/// The buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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pub fn blocking_read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
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self.blocking_transaction(address, &mut [Operation::Read(buffer)], true)
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self.blocking_transaction(address, &mut [Operation::Read(buffer)])
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}
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/// Write data to an I2C slave, then read data from the slave without
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@ -742,11 +685,7 @@ impl<'d, T: Instance> Twim<'d, T> {
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/// The buffers must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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pub fn blocking_write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Error> {
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self.blocking_transaction(
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address,
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&mut [Operation::Write(wr_buffer), Operation::Read(rd_buffer)],
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true,
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)
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self.blocking_transaction(address, &mut [Operation::Write(wr_buffer), Operation::Read(rd_buffer)])
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}
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/// Same as [`blocking_write_read`](Twim::blocking_write_read) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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@ -756,11 +695,7 @@ impl<'d, T: Instance> Twim<'d, T> {
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wr_buffer: &[u8],
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rd_buffer: &mut [u8],
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) -> Result<(), Error> {
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self.blocking_transaction_from_ram(
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address,
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&mut [Operation::Write(wr_buffer), Operation::Read(rd_buffer)],
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true,
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)
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self.blocking_transaction_from_ram(address, &mut [Operation::Write(wr_buffer), Operation::Read(rd_buffer)])
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}
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// ===========================================
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@ -770,7 +705,7 @@ impl<'d, T: Instance> Twim<'d, T> {
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/// See [`blocking_write`].
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#[cfg(feature = "time")]
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pub fn blocking_write_timeout(&mut self, address: u8, buffer: &[u8], timeout: Duration) -> Result<(), Error> {
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self.blocking_transaction_timeout(address, &mut [Operation::Write(buffer)], true, timeout)
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self.blocking_transaction_timeout(address, &mut [Operation::Write(buffer)], timeout)
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}
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/// Same as [`blocking_write`](Twim::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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@ -781,7 +716,7 @@ impl<'d, T: Instance> Twim<'d, T> {
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buffer: &[u8],
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timeout: Duration,
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) -> Result<(), Error> {
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self.blocking_transaction_from_ram_timeout(address, &mut [Operation::Write(buffer)], true, timeout)
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self.blocking_transaction_from_ram_timeout(address, &mut [Operation::Write(buffer)], timeout)
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}
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/// Read from an I2C slave.
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@ -790,7 +725,7 @@ impl<'d, T: Instance> Twim<'d, T> {
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/// and at most 65535 bytes on the nRF52840.
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#[cfg(feature = "time")]
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pub fn blocking_read_timeout(&mut self, address: u8, buffer: &mut [u8], timeout: Duration) -> Result<(), Error> {
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self.blocking_transaction_timeout(address, &mut [Operation::Read(buffer)], true, timeout)
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self.blocking_transaction_timeout(address, &mut [Operation::Read(buffer)], timeout)
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}
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/// Write data to an I2C slave, then read data from the slave without
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@ -809,7 +744,6 @@ impl<'d, T: Instance> Twim<'d, T> {
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self.blocking_transaction_timeout(
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address,
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&mut [Operation::Write(wr_buffer), Operation::Read(rd_buffer)],
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true,
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timeout,
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)
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}
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@ -826,7 +760,6 @@ impl<'d, T: Instance> Twim<'d, T> {
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self.blocking_transaction_from_ram_timeout(
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address,
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&mut [Operation::Write(wr_buffer), Operation::Read(rd_buffer)],
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true,
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timeout,
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)
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}
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@ -838,7 +771,7 @@ impl<'d, T: Instance> Twim<'d, T> {
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/// The buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
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self.transaction(address, &mut [Operation::Read(buffer)], true).await
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self.transaction(address, &mut [Operation::Read(buffer)]).await
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}
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/// Write to an I2C slave.
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||||
@ -846,12 +779,12 @@ impl<'d, T: Instance> Twim<'d, T> {
|
||||
/// The buffer must have a length of at most 255 bytes on the nRF52832
|
||||
/// and at most 65535 bytes on the nRF52840.
|
||||
pub async fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Error> {
|
||||
self.transaction(address, &mut [Operation::Write(buffer)], true).await
|
||||
self.transaction(address, &mut [Operation::Write(buffer)]).await
|
||||
}
|
||||
|
||||
/// Same as [`write`](Twim::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
|
||||
pub async fn write_from_ram(&mut self, address: u8, buffer: &[u8]) -> Result<(), Error> {
|
||||
self.transaction_from_ram(address, &mut [Operation::Write(buffer)], true)
|
||||
self.transaction_from_ram(address, &mut [Operation::Write(buffer)])
|
||||
.await
|
||||
}
|
||||
|
||||
@ -861,11 +794,7 @@ impl<'d, T: Instance> Twim<'d, T> {
|
||||
/// The buffers must have a length of at most 255 bytes on the nRF52832
|
||||
/// and at most 65535 bytes on the nRF52840.
|
||||
pub async fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Error> {
|
||||
self.transaction(
|
||||
address,
|
||||
&mut [Operation::Write(wr_buffer), Operation::Read(rd_buffer)],
|
||||
true,
|
||||
)
|
||||
self.transaction(address, &mut [Operation::Write(wr_buffer), Operation::Read(rd_buffer)])
|
||||
.await
|
||||
}
|
||||
|
||||
@ -876,11 +805,7 @@ impl<'d, T: Instance> Twim<'d, T> {
|
||||
wr_buffer: &[u8],
|
||||
rd_buffer: &mut [u8],
|
||||
) -> Result<(), Error> {
|
||||
self.transaction_from_ram(
|
||||
address,
|
||||
&mut [Operation::Write(wr_buffer), Operation::Read(rd_buffer)],
|
||||
true,
|
||||
)
|
||||
self.transaction_from_ram(address, &mut [Operation::Write(wr_buffer), Operation::Read(rd_buffer)])
|
||||
.await
|
||||
}
|
||||
}
|
||||
@ -999,13 +924,13 @@ impl<'d, T: Instance> embedded_hal_1::i2c::ErrorType for Twim<'d, T> {
|
||||
|
||||
impl<'d, T: Instance> embedded_hal_1::i2c::I2c for Twim<'d, T> {
|
||||
fn transaction(&mut self, address: u8, operations: &mut [Operation<'_>]) -> Result<(), Self::Error> {
|
||||
self.blocking_transaction(address, operations, true)
|
||||
self.blocking_transaction(address, operations)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embedded_hal_async::i2c::I2c for Twim<'d, T> {
|
||||
async fn transaction(&mut self, address: u8, operations: &mut [Operation<'_>]) -> Result<(), Self::Error> {
|
||||
self.transaction(address, operations, true).await
|
||||
self.transaction(address, operations).await
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user