diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index e32f19d91..e5cfee528 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -368,6 +368,7 @@ impl Registers {
             w.set_rfne(0, true); // Rx Fifo 0 New Msg
             w.set_rfne(1, true); // Rx Fifo 1 New Msg
             w.set_tce(true); //  Tx Complete
+            w.set_boe(true); // Bus-Off Status Changed
         });
         self.regs.ile().modify(|w| {
             w.set_eint0(true); // Interrupt Line 0
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index e31821ca2..563f542d4 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -44,53 +44,51 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
 
         let ir = regs.ir().read();
 
-        {
-            if ir.tc() {
-                regs.ir().write(|w| w.set_tc(true));
-            }
-            if ir.tefn() {
-                regs.ir().write(|w| w.set_tefn(true));
-            }
-
-            match &T::state().tx_mode {
-                TxMode::NonBuffered(waker) => waker.wake(),
-                TxMode::ClassicBuffered(buf) => {
-                    if !T::registers().tx_queue_is_full() {
-                        match buf.tx_receiver.try_receive() {
-                            Ok(frame) => {
-                                _ = T::registers().write(&frame);
-                            }
-                            Err(_) => {}
-                        }
-                    }
-                }
-                TxMode::FdBuffered(buf) => {
-                    if !T::registers().tx_queue_is_full() {
-                        match buf.tx_receiver.try_receive() {
-                            Ok(frame) => {
-                                _ = T::registers().write(&frame);
-                            }
-                            Err(_) => {}
-                        }
-                    }
-                }
-            }
+        if ir.tc() {
+            regs.ir().write(|w| w.set_tc(true));
+        }
+        if ir.tefn() {
+            regs.ir().write(|w| w.set_tefn(true));
         }
 
-        if ir.ped() || ir.pea() {
-            regs.ir().write(|w| {
-                w.set_ped(true);
-                w.set_pea(true);
-            });
+        match &T::state().tx_mode {
+            TxMode::NonBuffered(waker) => waker.wake(),
+            TxMode::ClassicBuffered(buf) => {
+                if !T::registers().tx_queue_is_full() {
+                    match buf.tx_receiver.try_receive() {
+                        Ok(frame) => {
+                            _ = T::registers().write(&frame);
+                        }
+                        Err(_) => {}
+                    }
+                }
+            }
+            TxMode::FdBuffered(buf) => {
+                if !T::registers().tx_queue_is_full() {
+                    match buf.tx_receiver.try_receive() {
+                        Ok(frame) => {
+                            _ = T::registers().write(&frame);
+                        }
+                        Err(_) => {}
+                    }
+                }
+            }
         }
 
         if ir.rfn(0) {
             T::state().rx_mode.on_interrupt::<T>(0);
         }
-
         if ir.rfn(1) {
             T::state().rx_mode.on_interrupt::<T>(1);
         }
+
+        if ir.bo() {
+            regs.ir().write(|w| w.set_bo(true));
+            if regs.psr().read().bo() {
+                // Initiate bus-off recovery sequence by resetting CCCR.INIT
+                regs.cccr().modify(|w| w.set_init(false));
+            }
+        }
     }
 }