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Add OTG core DMA address registers

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This commit is contained in:
ferris 2024-08-13 17:25:00 +02:00
parent 65b98f2f07
commit 0b87795937
1 changed files with 12 additions and 0 deletions
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12
embassy-usb-synopsys-otg/src/otg_v1.rs
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@ -272,6 +272,12 @@ impl Otg {
assert!(n < 12usize);
unsafe { Reg::from_ptr(self.ptr.add(0x0510usize + n * 32usize) as _) }
}
#[doc = "Host channel DMA address register"]
#[inline(always)]
pub const fn hcdma(self, n: usize) -> Reg<u32, RW> {
assert!(n < 12usize);
unsafe { Reg::from_ptr(self.ptr.add(0x0514usize + n * 32usize) as _) }
}
#[doc = "Device configuration register"]
#[inline(always)]
pub const fn dcfg(self) -> Reg<regs::Dcfg, RW> {
@ -364,6 +370,12 @@ impl Otg {
assert!(n < 16usize);
unsafe { Reg::from_ptr(self.ptr.add(0x0b10usize + n * 32usize) as _) }
}
#[doc = "Device OUT/IN endpoint DMA address register"]
#[inline(always)]
pub const fn doepdma(self, n: usize) -> Reg<u32, RW> {
assert!(n < 16usize);
unsafe { Reg::from_ptr(self.ptr.add(0x0b14usize + n * 32usize) as _) }
}
#[doc = "Power and clock gating control register"]
#[inline(always)]
pub const fn pcgcctl(self) -> Reg<regs::Pcgcctl, RW> {