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Merge pull request #3518 from chrenderle/lse-peripherals-clocked

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Enable user to choose to pass lse clock to peripherals
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Dario Nieuwenhuis 2024-11-18 11:36:05 +00:00 committed by GitHub
commit 050d3d1a09
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1 changed files with 26 additions and 0 deletions
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26
embassy-stm32/src/rcc/bd.rs
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@ -20,6 +20,9 @@ pub enum LseMode {
pub struct LseConfig { pub struct LseConfig {
pub frequency: Hertz, pub frequency: Hertz,
pub mode: LseMode, pub mode: LseMode,
/// If peripherals other than RTC/TAMP or RCC functions need the lse this bit must be set
#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
pub peripherals_clocked: bool,
} }
#[allow(dead_code)] #[allow(dead_code)]
@ -95,6 +98,8 @@ impl LsConfig {
lse: Some(LseConfig { lse: Some(LseConfig {
frequency: Hertz(32_768), frequency: Hertz(32_768),
mode: LseMode::Oscillator(LseDrive::MediumHigh), mode: LseMode::Oscillator(LseDrive::MediumHigh),
#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
peripherals_clocked: false,
}), }),
lsi: false, lsi: false,
} }
@ -148,6 +153,12 @@ impl LsConfig {
}, },
None => (false, false, None), None => (false, false, None),
}; };
#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
let lse_sysen = if let Some(lse) = self.lse {
Some(lse.peripherals_clocked)
} else {
None
};
_ = lse_drv; // not all chips have it. _ = lse_drv; // not all chips have it.
// Disable backup domain write protection // Disable backup domain write protection
@ -188,6 +199,10 @@ impl LsConfig {
} }
ok &= reg.lseon() == lse_en; ok &= reg.lseon() == lse_en;
ok &= reg.lsebyp() == lse_byp; ok &= reg.lsebyp() == lse_byp;
#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
if let Some(lse_sysen) = lse_sysen {
ok &= reg.lsesysen() == lse_sysen;
}
#[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))] #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))]
if let Some(lse_drv) = lse_drv { if let Some(lse_drv) = lse_drv {
ok &= reg.lsedrv() == lse_drv.into(); ok &= reg.lsedrv() == lse_drv.into();
@ -235,6 +250,17 @@ impl LsConfig {
}); });
while !bdcr().read().lserdy() {} while !bdcr().read().lserdy() {}
#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
if let Some(lse_sysen) = lse_sysen {
bdcr().modify(|w| {
w.set_lsesysen(lse_sysen);
});
if lse_sysen {
while !bdcr().read().lsesysrdy() {}
}
}
} }
if self.rtc != RtcClockSource::DISABLE { if self.rtc != RtcClockSource::DISABLE {