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https://github.com/embassy-rs/embassy.git
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Merge pull request #3023 from liarokapisv/i2s-ring-buffered
Revise I2S interface to ring-buffered.
This commit is contained in:
commit
0225c2a0f2
@ -1,12 +1,13 @@
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//! Inter-IC Sound (I2S)
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use embassy_futures::join::join;
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use embassy_hal_internal::into_ref;
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use stm32_metapac::spi::vals;
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use crate::dma::ChannelAndRequest;
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use crate::dma::{ringbuffer, ChannelAndRequest, ReadableRingBuffer, TransferOptions, WritableRingBuffer};
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use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
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use crate::mode::Async;
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use crate::pac::spi::vals;
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use crate::spi::{Config as SpiConfig, *};
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use crate::spi::{Config as SpiConfig, RegsExt as _, *};
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use crate::time::Hertz;
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use crate::{Peripheral, PeripheralRef};
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@ -19,6 +20,19 @@ pub enum Mode {
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Slave,
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}
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/// I2S function
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#[derive(Copy, Clone)]
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#[allow(dead_code)]
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enum Function {
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/// Transmit audio data
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Transmit,
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/// Receive audio data
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Receive,
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#[cfg(spi_v3)]
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/// Transmit and Receive audio data
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FullDuplex,
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}
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/// I2C standard
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#[derive(Copy, Clone)]
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pub enum Standard {
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@ -34,6 +48,30 @@ pub enum Standard {
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PcmShortSync,
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}
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/// SAI error
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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/// `write` called on a SAI in receive mode.
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NotATransmitter,
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/// `read` called on a SAI in transmit mode.
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NotAReceiver,
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/// Overrun
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Overrun,
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}
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impl From<ringbuffer::Error> for Error {
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fn from(#[allow(unused)] err: ringbuffer::Error) -> Self {
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#[cfg(feature = "defmt")]
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{
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if err == ringbuffer::Error::DmaUnsynced {
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defmt::error!("Ringbuffer broken invariants detected!");
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}
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}
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Self::Overrun
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}
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}
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impl Standard {
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#[cfg(any(spi_v1, spi_v3, spi_f1))]
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const fn i2sstd(&self) -> vals::I2sstd {
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@ -142,31 +180,62 @@ impl Default for Config {
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}
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}
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/// I2S driver writer. Useful for moving write functionality across tasks.
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pub struct Writer<'s, 'd, W: Word>(&'s mut WritableRingBuffer<'d, W>);
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impl<'s, 'd, W: Word> Writer<'s, 'd, W> {
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/// Write data to the I2S ringbuffer.
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/// This appends the data to the buffer and returns immediately. The data will be transmitted in the background.
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/// If thfre’s no space in the buffer, this waits until there is.
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pub async fn write(&mut self, data: &[W]) -> Result<(), Error> {
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self.0.write_exact(data).await?;
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Ok(())
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}
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/// Reset the ring buffer to its initial state.
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/// Can be used to recover from overrun.
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/// The ringbuffer will always auto-reset on Overrun in any case.
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pub fn reset(&mut self) {
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self.0.clear();
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}
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}
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/// I2S driver reader. Useful for moving read functionality across tasks.
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pub struct Reader<'s, 'd, W: Word>(&'s mut ReadableRingBuffer<'d, W>);
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impl<'s, 'd, W: Word> Reader<'s, 'd, W> {
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/// Read data from the I2S ringbuffer.
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/// SAI is always receiving data in the background. This function pops already-received data from the buffer.
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/// If there’s less than data.len() data in the buffer, this waits until there is.
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pub async fn read(&mut self, data: &mut [W]) -> Result<(), Error> {
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self.0.read_exact(data).await?;
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Ok(())
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}
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/// Reset the ring buffer to its initial state.
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/// Can be used to prevent overrun.
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/// The ringbuffer will always auto-reset on Overrun in any case.
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pub fn reset(&mut self) {
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self.0.clear();
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}
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}
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/// I2S driver.
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pub struct I2S<'d> {
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_peri: Spi<'d, Async>,
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pub struct I2S<'d, W: Word> {
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#[allow(dead_code)]
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mode: Mode,
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spi: Spi<'d, Async>,
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txsd: Option<PeripheralRef<'d, AnyPin>>,
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rxsd: Option<PeripheralRef<'d, AnyPin>>,
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ws: Option<PeripheralRef<'d, AnyPin>>,
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ck: Option<PeripheralRef<'d, AnyPin>>,
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mck: Option<PeripheralRef<'d, AnyPin>>,
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tx_ring_buffer: Option<WritableRingBuffer<'d, W>>,
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rx_ring_buffer: Option<ReadableRingBuffer<'d, W>>,
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}
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/// I2S function
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#[derive(Copy, Clone)]
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#[allow(dead_code)]
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enum Function {
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/// Transmit audio data
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Transmit,
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/// Receive audio data
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Receive,
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#[cfg(spi_v3)]
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/// Transmit and Receive audio data
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FullDuplex,
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}
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impl<'d> I2S<'d> {
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/// Create a transmitter driver
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impl<'d, W: Word> I2S<'d, W> {
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/// Create a transmitter driver.
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pub fn new_txonly<T: Instance>(
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peri: impl Peripheral<P = T> + 'd,
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sd: impl Peripheral<P = impl MosiPin<T>> + 'd,
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@ -174,18 +243,18 @@ impl<'d> I2S<'d> {
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ck: impl Peripheral<P = impl CkPin<T>> + 'd,
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mck: impl Peripheral<P = impl MckPin<T>> + 'd,
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txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
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txdma_buf: &'d mut [W],
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freq: Hertz,
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config: Config,
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) -> Self {
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into_ref!(sd);
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Self::new_inner(
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peri,
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new_pin!(sd, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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None,
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ws,
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ck,
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mck,
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new_dma!(txdma),
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new_pin!(mck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_dma!(txdma).map(|d| (d, txdma_buf)),
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None,
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freq,
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config,
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@ -193,42 +262,61 @@ impl<'d> I2S<'d> {
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)
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}
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/// Create a receiver driver
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/// Create a transmitter driver without a master clock pin.
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pub fn new_txonly_nomck<T: Instance>(
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peri: impl Peripheral<P = T> + 'd,
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sd: impl Peripheral<P = impl MosiPin<T>> + 'd,
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ws: impl Peripheral<P = impl WsPin<T>> + 'd,
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ck: impl Peripheral<P = impl CkPin<T>> + 'd,
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txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
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txdma_buf: &'d mut [W],
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freq: Hertz,
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config: Config,
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) -> Self {
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Self::new_inner(
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peri,
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new_pin!(sd, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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None,
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ws,
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ck,
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None,
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new_dma!(txdma).map(|d| (d, txdma_buf)),
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None,
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freq,
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config,
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Function::Transmit,
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)
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}
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/// Create a receiver driver.
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pub fn new_rxonly<T: Instance>(
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peri: impl Peripheral<P = T> + 'd,
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sd: impl Peripheral<P = impl MisoPin<T>> + 'd,
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ws: impl Peripheral<P = impl WsPin<T>> + 'd,
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ck: impl Peripheral<P = impl CkPin<T>> + 'd,
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mck: impl Peripheral<P = impl MckPin<T>> + 'd,
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#[cfg(not(spi_v3))] txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
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rxdma: impl Peripheral<P = impl RxDma<T>> + 'd,
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rxdma_buf: &'d mut [W],
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freq: Hertz,
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config: Config,
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) -> Self {
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into_ref!(sd);
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Self::new_inner(
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peri,
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None,
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new_pin!(sd, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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ws,
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ck,
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mck,
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#[cfg(not(spi_v3))]
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new_dma!(txdma),
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#[cfg(spi_v3)]
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new_pin!(mck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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None,
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new_dma!(rxdma),
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new_dma!(rxdma).map(|d| (d, rxdma_buf)),
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freq,
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config,
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#[cfg(not(spi_v3))]
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Function::Transmit,
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#[cfg(spi_v3)]
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Function::Receive,
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)
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}
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#[cfg(spi_v3)]
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/// Create a full duplex transmitter driver
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/// Create a full duplex driver.
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pub fn new_full_duplex<T: Instance>(
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peri: impl Peripheral<P = T> + 'd,
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txsd: impl Peripheral<P = impl MosiPin<T>> + 'd,
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@ -237,44 +325,144 @@ impl<'d> I2S<'d> {
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ck: impl Peripheral<P = impl CkPin<T>> + 'd,
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mck: impl Peripheral<P = impl MckPin<T>> + 'd,
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txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
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txdma_buf: &'d mut [W],
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rxdma: impl Peripheral<P = impl RxDma<T>> + 'd,
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rxdma_buf: &'d mut [W],
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freq: Hertz,
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config: Config,
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) -> Self {
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into_ref!(txsd, rxsd);
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Self::new_inner(
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peri,
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new_pin!(txsd, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(rxsd, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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ws,
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ck,
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mck,
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new_dma!(txdma),
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new_dma!(rxdma),
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new_pin!(mck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_dma!(txdma).map(|d| (d, txdma_buf)),
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new_dma!(rxdma).map(|d| (d, rxdma_buf)),
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freq,
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config,
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Function::FullDuplex,
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)
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}
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/// Write audio data.
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pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
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self._peri.read(data).await
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/// Start I2S driver.
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pub fn start(&mut self) {
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self.spi.info.regs.cr1().modify(|w| {
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w.set_spe(false);
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});
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self.spi.set_word_size(W::CONFIG);
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if let Some(tx_ring_buffer) = &mut self.tx_ring_buffer {
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tx_ring_buffer.start();
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set_txdmaen(self.spi.info.regs, true);
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}
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if let Some(rx_ring_buffer) = &mut self.rx_ring_buffer {
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rx_ring_buffer.start();
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// SPIv3 clears rxfifo on SPE=0
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#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
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flush_rx_fifo(self.spi.info.regs);
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set_rxdmaen(self.spi.info.regs, true);
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}
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self.spi.info.regs.cr1().modify(|w| {
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w.set_spe(true);
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});
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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self.spi.info.regs.cr1().modify(|w| {
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w.set_cstart(true);
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});
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}
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/// Write audio data.
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pub async fn write<W: Word>(&mut self, data: &[W]) -> Result<(), Error> {
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self._peri.write(data).await
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/// Reset the ring buffer to its initial state.
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/// Can be used to recover from overrun.
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pub fn clear(&mut self) {
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if let Some(rx_ring_buffer) = &mut self.rx_ring_buffer {
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rx_ring_buffer.clear();
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}
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if let Some(tx_ring_buffer) = &mut self.tx_ring_buffer {
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tx_ring_buffer.clear();
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}
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}
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/// Transfer audio data.
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pub async fn transfer<W: Word>(&mut self, read: &mut [W], write: &[W]) -> Result<(), Error> {
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self._peri.transfer(read, write).await
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/// Stop I2S driver.
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pub async fn stop(&mut self) {
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let regs = self.spi.info.regs;
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let tx_f = async {
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if let Some(tx_ring_buffer) = &mut self.tx_ring_buffer {
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tx_ring_buffer.stop().await;
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set_txdmaen(regs, false);
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}
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};
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let rx_f = async {
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if let Some(rx_ring_buffer) = &mut self.rx_ring_buffer {
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rx_ring_buffer.stop().await;
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set_rxdmaen(regs, false);
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}
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};
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join(rx_f, tx_f).await;
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#[cfg(any(spi_v3, spi_v4, spi_v5))]
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{
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if let Mode::Master = self.mode {
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regs.cr1().modify(|w| {
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w.set_csusp(true);
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});
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|
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while regs.cr1().read().cstart() {}
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}
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}
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regs.cr1().modify(|w| {
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w.set_spe(false);
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});
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self.clear();
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}
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/// Transfer audio data in place.
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pub async fn transfer_in_place<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
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self._peri.transfer_in_place(data).await
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/// Split the driver into a Reader/Writer pair.
|
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/// Useful for splitting the reader/writer functionality across tasks or
|
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/// for calling the read/write methods in parallel.
|
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pub fn split<'s>(&'s mut self) -> Result<(Reader<'s, 'd, W>, Writer<'s, 'd, W>), Error> {
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match (&mut self.rx_ring_buffer, &mut self.tx_ring_buffer) {
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(None, _) => Err(Error::NotAReceiver),
|
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(_, None) => Err(Error::NotATransmitter),
|
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(Some(rx_ring), Some(tx_ring)) => Ok((Reader(rx_ring), Writer(tx_ring))),
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}
|
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}
|
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|
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/// Read data from the I2S ringbuffer.
|
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/// SAI is always receiving data in the background. This function pops already-received data from the buffer.
|
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/// If there’s less than data.len() data in the buffer, this waits until there is.
|
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pub async fn read(&mut self, data: &mut [W]) -> Result<(), Error> {
|
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match &mut self.rx_ring_buffer {
|
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Some(ring) => Reader(ring).read(data).await,
|
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_ => Err(Error::NotAReceiver),
|
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}
|
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}
|
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|
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/// Write data to the I2S ringbuffer.
|
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/// This appends the data to the buffer and returns immediately. The data will be transmitted in the background.
|
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/// If thfre’s no space in the buffer, this waits until there is.
|
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pub async fn write(&mut self, data: &[W]) -> Result<(), Error> {
|
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match &mut self.tx_ring_buffer {
|
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Some(ring) => Writer(ring).write(data).await,
|
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_ => Err(Error::NotATransmitter),
|
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}
|
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}
|
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|
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/// Write data directly to the raw I2S ringbuffer.
|
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/// This can be used to fill the buffer before starting the DMA transfer.
|
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pub async fn write_immediate(&mut self, data: &mut [W]) -> Result<(usize, usize), Error> {
|
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match &mut self.tx_ring_buffer {
|
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Some(ring) => Ok(ring.write_immediate(data)?),
|
||||
_ => return Err(Error::NotATransmitter),
|
||||
}
|
||||
}
|
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|
||||
fn new_inner<T: Instance>(
|
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@ -283,23 +471,23 @@ impl<'d> I2S<'d> {
|
||||
rxsd: Option<PeripheralRef<'d, AnyPin>>,
|
||||
ws: impl Peripheral<P = impl WsPin<T>> + 'd,
|
||||
ck: impl Peripheral<P = impl CkPin<T>> + 'd,
|
||||
mck: impl Peripheral<P = impl MckPin<T>> + 'd,
|
||||
txdma: Option<ChannelAndRequest<'d>>,
|
||||
rxdma: Option<ChannelAndRequest<'d>>,
|
||||
mck: Option<PeripheralRef<'d, AnyPin>>,
|
||||
txdma: Option<(ChannelAndRequest<'d>, &'d mut [W])>,
|
||||
rxdma: Option<(ChannelAndRequest<'d>, &'d mut [W])>,
|
||||
freq: Hertz,
|
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config: Config,
|
||||
function: Function,
|
||||
) -> Self {
|
||||
into_ref!(ws, ck, mck);
|
||||
into_ref!(ws, ck);
|
||||
|
||||
ws.set_as_af(ws.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
|
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ck.set_as_af(ck.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
|
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mck.set_as_af(mck.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
|
||||
|
||||
let mut spi_cfg = SpiConfig::default();
|
||||
spi_cfg.frequency = freq;
|
||||
|
||||
let spi = Spi::new_internal(peri, txdma, rxdma, spi_cfg);
|
||||
let spi = Spi::new_internal(peri, None, None, {
|
||||
let mut config = SpiConfig::default();
|
||||
config.frequency = freq;
|
||||
config
|
||||
});
|
||||
|
||||
let regs = T::info().regs;
|
||||
|
||||
@ -390,22 +578,29 @@ impl<'d> I2S<'d> {
|
||||
w.set_i2se(true);
|
||||
});
|
||||
|
||||
#[cfg(spi_v3)]
|
||||
regs.cr1().modify(|w| w.set_spe(true));
|
||||
}
|
||||
let mut opts = TransferOptions::default();
|
||||
opts.half_transfer_ir = true;
|
||||
|
||||
Self {
|
||||
_peri: spi,
|
||||
txsd: txsd.map(|w| w.map_into()),
|
||||
rxsd: rxsd.map(|w| w.map_into()),
|
||||
ws: Some(ws.map_into()),
|
||||
ck: Some(ck.map_into()),
|
||||
mck: Some(mck.map_into()),
|
||||
Self {
|
||||
mode: config.mode,
|
||||
spi,
|
||||
txsd: txsd.map(|w| w.map_into()),
|
||||
rxsd: rxsd.map(|w| w.map_into()),
|
||||
ws: Some(ws.map_into()),
|
||||
ck: Some(ck.map_into()),
|
||||
mck: mck.map(|w| w.map_into()),
|
||||
tx_ring_buffer: txdma.map(|(ch, buf)| unsafe {
|
||||
WritableRingBuffer::new(ch.channel, ch.request, regs.tx_ptr(), buf, opts)
|
||||
}),
|
||||
rx_ring_buffer: rxdma.map(|(ch, buf)| unsafe {
|
||||
ReadableRingBuffer::new(ch.channel, ch.request, regs.rx_ptr(), buf, opts)
|
||||
}),
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d> Drop for I2S<'d> {
|
||||
impl<'d, W: Word> Drop for I2S<'d, W> {
|
||||
fn drop(&mut self) {
|
||||
self.txsd.as_ref().map(|x| x.set_as_disconnected());
|
||||
self.rxsd.as_ref().map(|x| x.set_as_disconnected());
|
||||
|
@ -311,8 +311,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
|
||||
}
|
||||
}
|
||||
|
||||
/// Set SPI word size. Disables SPI if needed, you have to enable it back yourself.
|
||||
fn set_word_size(&mut self, word_size: word_impl::Config) {
|
||||
pub(crate) fn set_word_size(&mut self, word_size: word_impl::Config) {
|
||||
if self.current_word_size == word_size {
|
||||
return;
|
||||
}
|
||||
@ -895,7 +894,7 @@ fn compute_frequency(kernel_clock: Hertz, br: Br) -> Hertz {
|
||||
kernel_clock / div
|
||||
}
|
||||
|
||||
trait RegsExt {
|
||||
pub(crate) trait RegsExt {
|
||||
fn tx_ptr<W>(&self) -> *mut W;
|
||||
fn rx_ptr<W>(&self) -> *mut W;
|
||||
}
|
||||
@ -983,7 +982,7 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
|
||||
}
|
||||
}
|
||||
|
||||
fn flush_rx_fifo(regs: Regs) {
|
||||
pub(crate) fn flush_rx_fifo(regs: Regs) {
|
||||
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
|
||||
while regs.sr().read().rxne() {
|
||||
#[cfg(not(spi_v2))]
|
||||
@ -997,7 +996,7 @@ fn flush_rx_fifo(regs: Regs) {
|
||||
}
|
||||
}
|
||||
|
||||
fn set_txdmaen(regs: Regs, val: bool) {
|
||||
pub(crate) fn set_txdmaen(regs: Regs, val: bool) {
|
||||
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
|
||||
regs.cr2().modify(|reg| {
|
||||
reg.set_txdmaen(val);
|
||||
@ -1008,7 +1007,7 @@ fn set_txdmaen(regs: Regs, val: bool) {
|
||||
});
|
||||
}
|
||||
|
||||
fn set_rxdmaen(regs: Regs, val: bool) {
|
||||
pub(crate) fn set_rxdmaen(regs: Regs, val: bool) {
|
||||
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
|
||||
regs.cr2().modify(|reg| {
|
||||
reg.set_rxdmaen(val);
|
||||
@ -1169,7 +1168,7 @@ impl<'d, W: Word> embedded_hal_async::spi::SpiBus<W> for Spi<'d, Async> {
|
||||
}
|
||||
}
|
||||
|
||||
trait SealedWord {
|
||||
pub(crate) trait SealedWord {
|
||||
const CONFIG: word_impl::Config;
|
||||
}
|
||||
|
||||
|
@ -1,13 +1,10 @@
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
use core::fmt::Write;
|
||||
|
||||
use defmt::*;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::i2s::{Config, I2S};
|
||||
use embassy_stm32::time::Hertz;
|
||||
use heapless::String;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::main]
|
||||
@ -15,6 +12,8 @@ async fn main(_spawner: Spawner) {
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
info!("Hello World!");
|
||||
|
||||
let mut dma_buffer = [0x00_u16; 128];
|
||||
|
||||
let mut i2s = I2S::new_txonly(
|
||||
p.SPI2,
|
||||
p.PC3, // sd
|
||||
@ -22,13 +21,13 @@ async fn main(_spawner: Spawner) {
|
||||
p.PB10, // ck
|
||||
p.PC6, // mck
|
||||
p.DMA1_CH4,
|
||||
&mut dma_buffer,
|
||||
Hertz(1_000_000),
|
||||
Config::default(),
|
||||
);
|
||||
|
||||
for n in 0u32.. {
|
||||
let mut write: String<128> = String::new();
|
||||
core::write!(&mut write, "Hello DMA World {}!\r\n", n).unwrap();
|
||||
i2s.write(&mut write.as_bytes()).await.ok();
|
||||
for i in 0_u16.. {
|
||||
i2s.write(&mut [i * 2; 64]).await.ok();
|
||||
i2s.write(&mut [i * 2 + 1; 64]).await.ok();
|
||||
}
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user